Advances in manufacturing technology have enabled larger and denser circuits to be placed on single semi-conductor integrated circuits. This is especially the case when the circuits are realised as regular or cellular structures, for example Random Access Memory. A major problem associated with high density device is that of testing. In order to maintain higher reliability, device test procedures need to provide good coverage of possible faults that occur in the integrated circuit.
One technique for providing testing of an integrated circuit is the so-called SIST architecture (signal integrity self-test architecture). The purpose of SIST architecture is to allow real time monitoring of important parameters which characterise the electrical behaviour of the integrated circuit. For example, monitors can be provided to detect cross talk, supply noise, substrate noise, temperature, switching activity, clock duty cycle etc. An SIST architecture has the advantage that testing can be performed before use during a test and debug process, and also during use (on-line).
FIG. 1 of the accompanying drawings is a block diagram illustrating an integrated circuit including previously considered Signal Integrity Self Test (SIST) architecture. The integrated circuit 1 comprises a number of functional cores or modules 2. These modules may perform analogue, digital or memory functions. For simplicity, it has been assumed that all cores are the same size. It will be readily appreciated that such techniques are not limited to an integrated circuit having cores of the same size. In addition, the normal interconnections and buses, which perform communication controls between the different functional cores, have been omitted from the diagram for the sake of clarity.
The integrated circuit 1 includes a monitor control block 4 which communicates with a number of monitors (not shown in FIG. 1) using a monitor selection bus 6. A reference and compare circuit 8 outputs a self-test signal from an output 10 in dependence upon received signals from the monitors. The monitors supply monitor output signals via a bus structure 12. The monitors are intended to be designed as standard cells, so that they can be located anywhere within each standard-cell block.
FIG. 2 of the accompanying drawings illustrates a functional core 2 from the integrated circuit of FIG. 1. The core 2 includes a plurality of monitors 16 connected to a decoder 14 and to the bus structure 12. In FIG. 2, the functional blocks relating to the function of the core have been omitted for the sake of clarity. FIG. 2 illustrates an exemplary core having four monitors 16. It will be readily appreciated that the core can be provided with any number of monitors in dependence upon the parameters to be measured. As mentioned above, different sensors are used to monitor different phenomena: cross talk, supply noise, substrate noise, temperature, switching activity, clock duty-cycle, etc.
The SIST architecture (FIG. 1) allows access to each individual monitor in a core using the monitor selection bus 6, which is controlled by the monitor control block 4. The monitor control block 4 includes a memory, which contains specific codes through which a certain monitor in a specific core can be selected. The output of the selected monitor is usually converted to a DC value or into a differential signal, which is then connected to the bus structure 12. This bus structure 12 may either be connected directly to a bondpad 10 of the integrated circuit, or, as shown, it may be connected to the reference and compare circuit 8. In one particular example, the reference and compare circuit 8 operates to determine whether the output signal from the monitor is within a certain allowed range. The reference and compare block 8 may contain reference values for each kind of monitor.
The monitor control block 4 can be placed on the integrated circuit, but can also be an external controller, for example a software program or an analysis tool. In all cases, it is necessary to provide a means to communicate between all monitors 16 and the monitor control block 4.
Such previously considered SIST architectures have the disadvantage that interfacing between the SIST monitors and the controller is complex. It is therefore desirable to provide a simplified interfacing technique for SIST architectures.